By David Naccache, Damien Sauveron (eds.)
ISBN-10: 3662438259
ISBN-13: 9783662438251
ISBN-10: 3662438267
ISBN-13: 9783662438268
This quantity constitutes the refereed lawsuits of the eighth IFIP WG 11.2 foreign Workshop on details safety conception and Practices, WISTP 2014, held in Heraklion, Crete, Greece, in June/July 2014. The eight revised complete papers and six brief papers awarded including 2 keynote talks have been conscientiously reviewed and chosen from 33 submissions. The papers were geared up in topical sections on cryptography and cryptanalysis, shrewdpermanent playing cards and embedded units, and privacy.
Read or Download Information Security Theory and Practice. Securing the Internet of Things: 8th IFIP WG 11.2 International Workshop, WISTP 2014, Heraklion, Crete, Greece, June 30 – July 2, 2014. Proceedings PDF
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Additional info for Information Security Theory and Practice. Securing the Internet of Things: 8th IFIP WG 11.2 International Workshop, WISTP 2014, Heraklion, Crete, Greece, June 30 – July 2, 2014. Proceedings
Example text
Considering these improvements we also provided practical insights on two devices employing an ARM Cortex-A processor. We performed theoretical investigations of attacking different key-chunk sizes and presented potential pitfalls. Our practical investigations on ARM-based devices showed that attacking one-byte chunks seems to be the best choice for resource-constrained devices. Furthermore, these investigations showed that the minimum timing information [2] does not improve the cache timing attack on the ARM Cortex-A devices at all.
Their idea is to capture only one single measurement sample without noise, which is then stored and used for the correlation later on. They successfully launched their attack against a Pentium Dual-Core and a Pentium Core 2 Duo processor. However, contrary to their conclusion that this approach significantly improves the timing attack on Pentium processors, our results indicate that this approach does not even work at all on ARM Cortex-A processors. The reasons for this approach to fail on the ARM Cortex-A processor are potentially manifold.
First, Aly and ElGayyar [2] attacked an AES implementation employing 4-Tables. In contrast, we attacked an implementation employing 5 T-tables. Second, according to our understanding, gathering the minimum encryption time misses potential useful information. As Neve et al. [15] put it, Bernstein’s timing attack implicitly searches for cache evictions due to work done on the attacked device. Such cache evictions lead to cache misses within the encryption function and, thus, to slower encryptions.
Information Security Theory and Practice. Securing the Internet of Things: 8th IFIP WG 11.2 International Workshop, WISTP 2014, Heraklion, Crete, Greece, June 30 – July 2, 2014. Proceedings by David Naccache, Damien Sauveron (eds.)
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