Get Memory Management. Algor. and Impl. in C-C++ PDF

By Bill Blunden

ISBN-10: 1556223471

ISBN-13: 9781556223471

Reminiscence administration: Algorithms and Implementation in C/C++ provides numerous concrete implementations of rubbish assortment and specific reminiscence administration algorithms. each implementation is complemented by way of an in-depth presentation of idea, through benchmark exams, an entire directory of C/C++ resource code, and a dialogue of every implementation s trade-offs. learn the way reminiscence is controlled on the point by means of the processor notice the ways that diversified working platforms benefit from processor amenities to supply reminiscence companies through the method name interface. know how improvement libraries and run-time platforms construct upon the working procedure companies to control reminiscence on behalf of consumer functions. know about 5 whole reminiscence administration subsystems that make the most of either particular and automated assortment algorithms.

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The CR4 register is used to enable a couple of advanced mechanisms. For example, the PAE flag enables four extra address lines when it is set. This would bring the number of address lines to 36. Note that the PG flag must be set in CR0 in order for PAE to be effective. Another flag of interest is the PSE bit. If PSE is cleared to zero, the page size is 4KB. If PSE is set, the page size is 4MB. If both PAE and PSE are set, the page size is 2MB. Paging as Protection Traditionally, paging has been used to artificially expand the amount of memory to which a processor has access.

Back in the iron age, when mainframes walked the earth, it was called the core. The storage provided by these chips is volatile, which is to say that data in the chips is lost when the power is switched off. There are various types of RAM: n DRAM n SDRAM n SRAM 3 Chapter 1 Memory Management Mechanisms 4 Chapter 1 n VRAM Dynamic RAM (DRAM) has to be recharged thousands of times each second. Synchronous DRAM (SDRAM) is refreshed at the clock speed at which the processor runs the most efficiently.

The IDTR and TR registers are used to manage hardware interrupts and multitasking. This book is focused on pure memory management, so I will not discuss these registers in any detail. If you happen to be interested, I recommend that you pick up the Intel manual referenced at the end of this chapter. Earlier I mentioned that segment descriptors store the base linear address of the memory segment they describe. However, they also hold a whole lot of other metadata. 12 should give you a better idea of what lies within a segment descriptor.

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