By Derrick Morris
ISBN-10: 0333257502
ISBN-13: 9780333257500
ISBN-10: 1349161039
ISBN-13: 9781349161034
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Sample text
Output from the simulator takes the form of timing diagrams, fault monitoring which identifies timing errors such as short pulses, and detailed listings showing changes of state of network signals as they occur. The central feature of the simulator itself is a time-ordered event list. Entries in this list indicate that, as a result of a change of state at the inputs to agate, a new output state for that gate has been predicted. When an entry is removed from the top of the list,. the predicted signal change can 'occur'.
Thus each gate can drive two series matched 75 ohm lines from each output, and each line is capable of driving up to two input loads at the receiving end. Associated with each output is a group of 44 resistors, the output load resistor (exeluded from the integrated circuit itself to reduee power dissipation within the package) and two series matehing resistors. These are fabricated on a single ceramic chip in thiek film technology and over 45 000 such chips are used in the MU5 system. 6 ns per input load is introduced.
In the event 52 of 3. hardware fai 1 ure in one or more stacks, a Fail-soft capability allows the store to be re-configured, so that the best use can be made of the remaining stacks. Thus, for a read request to a given stack, the appropriate twelve address bits, as selected by the Fail-soft logic in the Local Store Interface, are copied into the Address Buffer, and the eleven least significant digits select 3. line in the stack for reading. The da ta from all 144 digit wires is copied into the Data Buffer and the least significant address digit then selects the even or odd half.
The MU5 Computer System by Derrick Morris
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